The present invention relates generally to semiconductor devices, and more particularly to the formation of FinFET devices with reduced gate-to-contact end parasitic capacitance.
Semiconductor devices generally include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. To improve the performance of the circuits, low k dielectric materials, having a dielectric constant of less than silicon dioxide, are used between circuits as inter-layer dielectric (ILD) to reduce capacitance. Interconnect structures made of metal lines are usually formed in and around the ILD material to connect elements of the circuits. Within a typical interconnect structure, metal lines run parallel to the semiconductor substrate. An interconnect structure may consist of multilevel or multilayered schemes, such as, single or dual damascene wiring structures.
Gate-to-contact parasitic capacitance in integrated circuits (ICs) may contribute to increased power consumption and reduced device performance and speed. Typically, spacers formed on gate sidewalls employ silicon nitride; however, silicon nitride has a relatively high dielectric constant and thus, results in high gate parasitic capacitances. Spacers composed of an oxide material have been used to reduce the parasitic capacitance. Spacers composed of a nitride material can also be used, and later removed and replaced with lower-capacitance materials, such as an oxide. Such parasitic capacitances can increase device power consumption and can impact device performance.